The present disclosure relates to a memory controller, and more particularly, to a memory controller for receiving differential data strobe signals and an application processor having the memory controller.
A memory controller receives a differential signal used for an internal operation thereof and processes the differential signal. Regarding the type of the differential signal, differential DQS signals are used for a data receiving operation ensure the quality of a high-speed memory operation. The differential DQS signals have a phase difference of about 180 degrees.
However, the differential DQS signals are not synchronized with a clock applied to memory by the memory controller. As an example, a variation in a delay of the differential DQS signals occurs due to variations in voltage and temperature, thereby causing deterioration of the quality of the data receiving operation. In order to prevent this, a DQS cleaning method using a gate training process has been suggested. However, since the DQS cleaning method is required to ensure the accuracy of a high frequency clock up to one clock cycle in a high-speed memory interface, the difficulty of designing a semiconductor device to ensure the accuracy of such a clock increases, and thus, a size of the semiconductor device increases.